This invention is in the field of non-volatile memory integrated circuits. Embodiments of this invention are more specifically directed to testing of electrically programmable and erasable non-volatile memory for reliability parameters.
Non-volatile solid-state read/write memory devices are now commonplace in many electronic systems, particularly in portable electronic devices and systems. A common technology for realizing non-volatile solid-state memory devices involves the trapping of charge at or near the gate element of a metal-oxide-semiconductor (MOS) transistor in the programmable memory cell. In conventional electrically erasable programmable “read-only” memory (EEPROM) devices, programming by way of this charge-trapping mechanism is performed by biasing the transistor so that electrons tunnel through a thin dielectric film onto an electrically isolated transistor gate element (i.e., the “floating-gate” electrodes), or in some technologies, within the gate dielectric layer or at the silicon-dielectric interface. Depending on the construction of the transistor, the tunneling mechanism may be Fowler-Nordheim tunneling or channel “hot” carrier injection. In any case, the trapped electrons at the gate region raise the apparent threshold voltage of the memory cell transistor (for n-channel devices), as compared with the threshold voltage for the state in which no electrons are trapped at the gate. The stored state can be read by sensing the presence or absence of source-drain conduction under bias.
Modern EEPROM devices are “erasable” in that the memory cell transistors can be biased to remove the electrons from the floating gate, by reversing the tunneling mechanism. Some EEPROM memory devices are of the “flash” type, in that a large number (a “block”) of memory cells are simultaneously erased in a single operation. Conventional EEPROM memories can be arranged in a “NOR” fashion, which permits individual cells in each column to be separately and individually accessed. Flash EEPROM memories are also now commonly arranged as “NAND” memory, in which the source/drain paths of a group of memory cells in a column are connected in series. NAND memories can be constructed with higher density, but require all of the cells in a group to be biased to access any one of the cells in that group.
FIG. 1a illustrates a typical manner in which the stored state of an EEPROM cell is sensed in conventional integrated circuits. In this example, floating-gate memory cell 2j,k is a non-volatile memory cell, for example of the EEPROM or flash type, that resides in row j and column k of a memory array and that is being addressed in this read operation. The memory cells in that memory array may be arranged in either a NOR or NAND type, as known in the art; the unselected cells are not shown in FIG. 1a for the sake of clarity. In this example, EEPROM cell 2j,k consists essentially of a single n-channel metal-oxide-semiconductor (MOS) transistor in which a floating gate electrode is physically disposed between a control gate and the channel region of the transistor. The control gate of this transistor of cell 2j,k receives a control gate voltage VCGj for its row j, and its source and drain are coupled to bit line BLk for its column k as appropriate for its NOR or NAND configuration. The specific physical arrangement of the floating gate relative to the other elements of EEPROM cell 2 can vary depending on the particular design, as known in the art.
In conventional floating gate EEPROMs such as that including cell 2j,k of FIG. 1a, an absence of trapped electrons at the floating gate electrode is considered as the “erased” state of the memory cell, and will be evident by the (n-channel) floating-gate transistor having a low threshold voltage. The “programmed” state in which electrons are trapped at the floating gate results in the floating-gate transistor having a high threshold voltage. Programming of cell 2j,k is typically performed by the application of a sufficient drain-to-source drive along with a high voltage at the control gate that capacitively couples to the floating gate electrode. Under this bias, electrons can tunnel from the transistor drain or channel region to become trapped at the floating gate electrode, changing the threshold voltage of the device as a result. Erase of cell 2j,k is accomplished by application of the opposite bias between the transistor channel region and the control gate, which draws the trapped electrons from the floating gate electrode.
To read the state of EEPROM cell 2j,k, a bit line voltage VBLk is coupled to one end of bit line BLk for the selected column k, and appears at the drain of the floating-gate transistor of cell 2j,k. In addition, a control gate voltage VCGj at a level V_Read is applied to the control gates of cells 2 in selected row j. The source of selected cell 2j,k is coupled to one input of sense amplifier 4, which receives a reference current IREF_Read at its other input from reference generator 6. Sense amplifier 4 compares the bit cell current BCCBit conducted by bit line BLk through the selected cell 2j,k with the reference current IREF_Read, and presents a logic level at its output DATAout in response to that comparison.
Accordingly, the level at output DATAout reflects whether selected cell 2j,k is in its programmed state or its erased state. As mentioned above, the programmed state of cell 2j,k results in the floating-gate transistor having a high enough threshold voltage that the applied voltage V_read at the control gate will fail to turn the transistor on, as reflected by the bit cell current BCCBit being below the reference current IREF_Read, resulting in a “0” logic level at output DATABit of sense amplifier 4. Conversely, because the floating-gate transistor has a low threshold voltage in the “erased” state of cell 2j,k, a control gate voltage of V_read is sufficient to turn on the transistor, which is reflected by the bit cell current BCCBit being above the reference current IREF_Read and, in turn, sense amplifier 4 driving its output DATAout to a “1” logic level.
As known in the art, variations in programmability among the EEPROM cells of a device are present due to structural variations among the floating gate transistors, and manufacturing and processing variations from wafer to wafer. As a result, some EEPROM cells in a population will tend to not program or erase as strongly as others in the population; these weaker cells are of course vulnerable to causing data errors as their programmability and data retention weaken even further over operating life. The binary information provided merely by reading the stored state of EEPROM cells provides little insight into the strength or weakness of the cells. Accordingly, test methods have been developed to determine the programmability of EEPROM cells in an integrated circuit, and if possible, to identify those cells that are most vulnerable, as will now be discussed with reference to FIG. 1b. 
According to one approach described in Nafziger et al., “Method for efficient flash bit cell current compression in deeply erased bits”, 16th Intl Symp. on Quality Electronic Design (IEEE, 2015), pp. 77-81, incorporated herein by reference, the bit cell current BCCBit for the weakest and strongest cell 2 in an array can be determined by modulating the reference current IREF_Read applied to sense amplifier 4 in reading the cells 2 in the array. FIG. 1b illustrates the relationship between control gate voltage VCG and the bit cell current BCCBit for a population of EEPROM cells 2 including both erased bits (plots 10) and programmed bits (plots 12). As evident from plots 12, the programmed cells in this population exhibit very little bit cell current BCCBit, well below the nominal reference current level IREF_Read, when read at the nominal control gate voltage V_Read; conversely, plots 10 show that the erased cells exhibit bit cell currents BCCBit above IREF_Read when read at the nominal control gate voltage V_Read. The most and least erased cells can be identified by sweeping the reference current IREF applied to sense amplifiers 4 during reads at control gate voltage V_Read. In this example, plot 10max corresponds to the cell that exhibits the highest bit cell current BCCMax at the nominal read voltage V_Read; this cell is the most erased bit in the array. Conversely, plot 10min corresponds to the erased cell that exhibits the lowest bit cell current BCCMin at the nominal read voltage V_Read; this cell is the least erased bit in the array.
Another conventional approach to evaluating the weakest and strongest cells in an EEPROM array involves the sweeping of the control gate voltage VCG applied to the control gates of cells 2 during reads at a constant level IREF_Read of the reference current applied to sense amplifiers 4, for example as described in Cai et al., “Threshold Voltage Distribution in MLC NAND Flash Memory: Characterization, Analysis, and Modeling”, Proc. of the Conf. on Design, Automation, and Test in Europe (IEEE, 2013), pp. 1285-90. As evident from FIG. 1b, it has been observed that some programmed EEPROM cells do not exhibit weaker programmability at the relatively low control gate voltages (e.g., V_Read) typically applied in normal read operations, but can be differentiated at higher control gate voltages. For example, plot 12min corresponds to a cell 2 that conducts a bit cell current IREF_Read at a relatively low control gate voltage VTMin as compared with normal cells exemplified by plots 12a, 12b. 
The ability to test the “goodness” or strength of EEPROM cells by way of these BCC and VT screens is useful both at the time of manufacture, and also during the operating life of the integrated circuit, for example as part of a “built-in self-test” (BIST) routine executed on power-up of the integrated circuit. In either case, the test necessarily requires knowledge of the expected data for each cell under test. Typically, a regular data pattern such as all 0's, all 1's, checkerboard, diagonals, or the like that is either trivial or algorithmically generated is used, in order to minimize the requirements for local memory resources to store the expected data for the arrays.
Because of the convenience and efficiency of modern flash EEPROM memories, it is now desirable and commonplace to embed EEPROM memory within larger scale integrated circuits, such as those including modern complex microprocessors, microcontrollers, digital signal processors, and other large-scale logic circuitry. In addition to bulk non-volatile data storage, however, embedded EEPROM resources in microcontroller architectures are used to store executable software routines, configuration data, trim codes for on-die peripheral functions, and the like. Particularly in microcontroller architectures, some of these non-volatile memory resources may be pre-loaded by the manufacturer of the microcontroller with compiled assembly code and other irregular, non-algorithmically determinable, data sets. The irregularity and uniqueness of the pre-stored data in these embedded EEPROM resources render it difficult to carry out the BCC and VT reliability screening described above, especially in the BIST context. More specifically, in order for a BIST reliability screen to directly determine which memory cell is the weakest erased cell (i.e., exhibits the lowest bit cell current BCCMin) or which is the weakest programmed cell (i.e., exhibits the lowest threshold voltage VTMin), additional on-chip memory of the same size as the EEPROM array must be provided to store the irregular data set that is stored in the EEPROM array under test.
One known indirect approach for performing BCC and VT reliability screening of embedded EEPROM arrays that are storing irregular (i.e., not algorithmically determinable) data is illustrated in FIG. 2. In this example, plot 15 illustrates the actual distribution of bit cell currents BCC for each of the erased (i.e., “1” data state) cells in an EEPROM array, arranged by ascending memory address; these bit cell currents BCC correspond to the minimum reference current IREF at which the corresponding cells will fail to return the correct “1” data state when read. A similar plot (not shown) could be made for the programmed (i.e., “0” data state) cells. Because the data pattern is irregular, however, and because a copy of that irregular data pattern is not known by the device according to this indirect method, plot 15 is unknown at the time of the reliability screen according to this method; rather, the minimum bit cell current BCCMin of the least erased cell 2wk1 is the unknown to be determined.
In this conventional approach, a binary search of reference current IREF levels is performed, with the entire EEPROM array read at each of those IREF levels. First, the entire memory array is read at a reference current IREF_1 at which all erased cells are expected to provide the correct “1” data state. For example, reference current level IREF_1 for this first read may be the nominal level IREF_Read used in read operations during normal use. Based on the data read in this first read of the array, a checksum is calculated against which subsequent reads of the array will be compared. The EEPROM array is then read at a reference current level IREF_2 at which many, if not all, of the erased cells are expected to not provide the correct “1” data state, for example at the expected level of the most erased cell (bit cell current BCCMax as shown in FIG. 1b). The checksum calculated from these data will not match the correct checksum obtained at reference current level IREF_1. A next read of the array is performed at a reference current IREF_3 at the midpoint between the expected pass level IREF_1 and the expected fail level IREF_2, and the checksum from this read is compared against the correct checksum from the read at IREF_1. If the checksums match, the next reference current IREF will be at the midpoint between the failing level IREF_2 and the level IREF_3 at this most recent read. If the checksums do not match, as in the example of FIG. 2, the next reference current IREF_4 is at the midpoint between the passing level IREF_1 and the level IREF_3 of the most recent previous read. The process is repeated, modifying the reference current IREF in this manner, until the desired number of iterations have been performed. The minimum bit level current BCCMin can be considered as the lowest reference current IREF level at which the correct checksum was returned following a read of the array.
Additionally, or in the alternative, a similar binary search of the control gate voltages VCG may be carried out, for example to identify the minimum threshold voltage VTMin of the programmed “0” bits.
This conventional approach requires significant test time, however. Because an image of the programmed irregular data is not available or used in this screen, the pass/fail determination can be made only by reading the entire EEPROM array at each reference level in order to derive a checksum over the array. For the simple example of FIG. 2, five reads of the entire memory array are required, which can consume significant test time in modern embedded microcontrollers, especially during the power-up BIST sequence of a modern device. In addition, this approach does not provide a precise determination of the minimum bit level current BCCMin or minimum control gate voltage VTMin, but instead only provides an estimate of that value at a resolution defined by the number of steps in the binary search (i.e., the number of reads of the full array). Furthermore, this conventional indirect approach cannot identify the weakest cell, because the pass/fail determination is made by comparing checksums.